Clock gating is a power management technique used to reduce the power consumption associated with a clock in an integrated circuit. In addition to reducing power consumption, a clock gating system should provide consistent system performance. The clock gating process is implemented by placing various logic components within the integrated circuit in an idle state whenever they are not conducting data transactions. This is accomplished by preventing a particular logic component from receiving system clock pulses (i.e., gating the system clock). Further, while in the idle state, the logic component must be accorded access to the system clock (i.e., ungating the system clock (or waking up the logic component)) whenever it is ready to receive data.
FIG. 1 is a block diagram of an exemplary clock gating circuit coupled to a logic circuit. The clock gating circuit includes a d-latch and an and-gate. The logic circuit continuously transmits a status signal to the data input of the d-latch. Whenever the logic circuit is receiving data, the status signal is transmitted to the d-latch as a logical zero. Accordingly, the and-gate is activated and a logic clock pulse (LOGIC CLK) is transmitted from the clock gating circuit to the logic circuit. LOGIC CLK, in turn, drives the data transactions conducted at the logic circuit.
Whenever the logic circuit is not receiving data that is to be acted upon by the logic circuit, the logic circuit enters a sleep state and a logic 1 is transmitted to the input of the d-latch. In this case, the and-gate, is deactivated and LOGIC CLK is gated. The logic circuit remains in the sleep state as long as the status signal remains a logical one (i.e., the logic circuit is not receiving data). However, once the logic circuit is ready to wake up, a logic 0 is transmitted to the clock gating circuit. As a result, LOGIC CLK is ungated.
The problem with typical clock gating circuits is that there is usually a one or two clock delay from the time the logic circuit enters the idle state until LOGIC CLK is actually gated. Similarly, there is a one or two clock delay from the time the logic circuit is ready to wake up before LOGIC CLK is ungated. Thus, the use of typical clock gating circuits result in inefficient clock performance since one or more clock cycles are wasted before gating and ungating the clock. Therefore, an efficient method of gating and ungating logic circuits within an integrated circuit is desired.